1. Field of the Invention
The present invention relates to a semiconductor device having a gate structure in a trench.
2. Description of the Related Art
As a conventional power MOSFET, a DMOS (Double diffusion MOS) structure has been generally used. However, such a structure has the following problems when increasing the integration density by applying a fine pattern structure thereto.
(1) A diffusion length of a lateral direction for forming a base region is limited to a pitch of design layout.
(2) A parasitic JFET (Junction FET) formed between contiguous base regions narrows a path through which a current vertically flows, thereby to increase a resistance component of a buffer layer.
The tendencies of the problems (1) and (2) are enhanced when the design pitch is set to be small. As a result, since an optimum value is present in the layout, a decrease in on-resistance may be limited even if the integration density is increased. However, when the area of an element is increased to decrease the on-resistance, a production cost may be increased, and problems such as an unstable operation of the element or parasitic oscillation caused by parallel connection may be caused.
For this reason, a MOSFET having a gate formed in a trench, a source formed above the gate, and a substrate used as a drain has been developed. In this MOSFET using the trench, the above two drawbacks can be eliminated to improve the integration density and the decrease in the on-resistance.
In the MOSFET having the gate formed in the trench, the on-resistance can be decreased by increasing the depth of the trench. However, when the depth of the trench is increased, a breakdown voltage between the bottom of the trench and the drain may be lowered.